Product Summary

The HY57V281620ETP-H is a 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O - Hynix Semiconductor. It is ideally suited for the memory applications which require wide data I/O and high bandwidth. The HY57V281620ETP-H is organized as 4 banks of 2,097,152 x 16. The HY57V281620ETP-H is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

Parametrics

HY57V281620ETP-H absolute maximum ratings: (1)Ambient Temperature TA: 0 to 70℃; (2)Storage Temperature TSTG: -55℃ to 125℃; (3)Voltage on Any Pin relative to VSS VIN, VOUT: -1.0 to 4.6V; (4)Voltage on VDD relative to VSS VDD, VDDQ: -1.0V to 4.6V; (5)Short Circuit Output Current IOS: 50mA; (6)Power Dissipation PD: 1W; (7)Soldering Temperature/Time TSOLDER: 260/10 ℃/Sec.

Features

HY57V281620ETP-H features: (1)Voltage: VDD, VDDQ 3.3V supply voltage; (2)All device pins are compatible with LVTTL interface; (3)54 Pin TSOPII (Lead or Lead Free Package); (4)All inputs and outputs referenced to positive edge of system clock; (5)Data mask function by UDQM, LDQM; (6)Internal four banks operation; (7)Auto refresh and self refresh; (8)4096 Refresh cycles / 64ms; (9)Programmable Burst Length and Burst Type; (10)Programmable CAS Latency; 2, 3 Clocks; (11)Burst Read Single Write operation.

Diagrams

HY57V281620ETP-H block diagram

HY57V121620(L)T
HY57V121620(L)T

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Negotiable 
HY57V161610D
HY57V161610D

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Negotiable 
HY57V161610D-I
HY57V161610D-I

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Negotiable 
HY57V161610E
HY57V161610E

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Negotiable 
HY57V161610ET-I
HY57V161610ET-I

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Negotiable 
HY57V161610ETP-I
HY57V161610ETP-I

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Data Sheet

Negotiable